1) Field
This embodiment relates to a timing verification method, a timing verification apparatus, a timing verification program suitable for use with layout design of a semiconductor integrated circuit wherein power supply voltage drop (IR-Drop) analysis is performed.
2) Description of the Related Art
In recent years, in timing verification in layout design of a semiconductor integrated circuit (LSI), power supply voltage drop (IR-Drop) analysis is performed and timing analysis is performed taking a result of the power supply voltage drop analysis into consideration to perform circuit changing [generally called ECO (Engineering Change Orders)] for timing adjustment.
Here, FIG. 9 is a flow chart illustrating a general design process including such processes (timing ECO processes) as IR-Drop analysis, timing analysis and ECO.
First, a net list is produced by logic synthesis (step A10).
Then, a layout process, that is, arrangement of cells and wiring, are performed based on the net list (step A20). It is to be noted that arrangement wiring data of the laid out circuit are stored into an arrangement wiring database (DB).
Thereafter, resistance values and capacitance values (RC) of the laid out circuit are extracted (RC Extraction; step A30). It is to be noted that the extracted resistance values and capacitance values are stored as a SPEF (Standard Parasitic Exchange Format) file into a storage unit.
Then, IR-Drop analysis is performed for the entire laid out circuit using the arrangement wiring data stored in the arrangement wiring database, the extracted resistance values and capacitance values and so forth (step A40). It is to be noted that a result of the analysis is stored into an IR-Drop analysis database.
Then, estimate calculation of delay values is performed based on the extracted resistance values and capacitance values (delay calculation) (step A50). Thereafter, timing analysis, for example, by a static timing analyzer (STA) is performed using the delay values estimated by the delay calculation and the result of the IR-Drop analysis (step A50).
If a timing error is found as a result of the timing analysis, then timing adjustment for correcting a portion at which the timing error appears is performed, and an ECO list for indicating circuit changing [for example, addition of a cell (for example, insertion of a buffer), deletion of a cell, resizing of a cell (gate sizing; for example, changing of the power type)] is produced (step A60).
Thereafter, the processes at steps A20 to A60 (timing ECO processes) are repetitively performed until the timing error is eliminated (that is, the ECO list disappears).
It is to be noted that, for example, Japanese Patent Laid-Open No. 2004-118802 discloses that, in layout design of a semiconductor integrated circuit, power supply voltage drop (IR-Drop) analysis is performed after a layout process is performed, and timing analysis is performed taking a result of the IR-Drop analysis into consideration. Further, Japanese Patent Laid-Open No. 2003-256497 discloses that the voltage drop amount for each of instances (cells) is calculated when timing analysis is performed.